| Master Thesis - Oregon State University | |
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Design and Evaluation of On-line Arithmetic Modules and Networks for Signal
Processing Applications on FPGAs Abstract Several papers propose the use of on-line arithmetic for signal processing applications implemented on FPGAs. Although those papers provide reasonable arguments for the use of on-line arithmetic, they give only inadequate or incomplete comparisons of the proposed on-line designs to other state of the art solutions on FPGAs. In this thesis, the design, implementation and evaluation of on-line modules and networks for DSP applications, using FPGAs as the target technology, are shown. The presented designs of the modules are highly optimized for the target hardware, which allows a significant increase in efficiency compared to standard on-line designs. The design process for the networks of on-line modules is described in detail, and a methodology to analyze the dataflow and timing is presented. A comparison of on-line signal processing solutions with other approaches, that are available as IP building blocks or components, is given. It is shown that on-line designs are better in terms of latency but that they can not compete in terms of throughput and area for basic applications like FIR filters. However, it is also shown that on-line designs are able to overtake other approaches as the applications become more sophisticated, e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches, such as serial distributed arithmetic. For these applications, on-line arithmetic shows, compared to other designs, a lower latency and a significant area reduction, while maintaining a high throughput. Several properties of algorithms for which on-line arithmetic is advantageous are identified in this thesis. With this information, it is possible to determine if an on-line solution for an application should be considered. The conclusions are based on experimental data collected using CAD tools for the Xilinx XC4000 family of chips. All the designs are synthesized for the same type of devices for comparison, avoiding rough estimates of the system performance. This generates a more reliable comparison allowing designers to decide between on-line or conventional approaches for their DSP designs. Download as PDF (1MB) |
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| Publications | |
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Reto Galli and Alexandre F. Tenca, "Design and evaluation of on-line arithmetic for signal
processing applications on FPGAs", Proceedings of SPIE, Advanced Signal Processing Algorithms,
Architectures, and Implementations IV, vol.4474, August 2001 Download as PDF (237KB) Reto Galli and Alexandre F. Tenca, "A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 12, Issue 1, Pages: 52-66, January 2004 Download as PDF (332KB) |
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